1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly, to a semiconductor device having an impurity region formed by ion implantation with a gate electrode as a mask, and a method of manufacturing thereof.
2. Description of the Background Art
An MOS transistor is well known as one type of a semiconductor device. FIG. 7 is a sectional view of a conventional P channel MOS transistor comprising a gate electrode. Referring to FIG. 7, a P channel MOS transistor comprises an N type silicon substrate 11, element isolation oxide films 12 formed on N type silicon substrate 11 with a predetermined distance therebetween for element isolation, p.sup.+ impurity regions 15 with a predetermined distance therebetween formed between element isolation oxide film 12, and a polycrystal silicon layer 14 forming a gate electrode provided between p.sup.+ impurity regions 15 with a gate oxide film 13 thereunder. A conventional P channel MOS transistor has a gate electrode formed by polycrystal silicon layer 14.
FIG. 8 is an enlarged sectional view of the gate electrode of FIG. 7 for explaining the crystal structure. Referring to FIG. 8, polycrystal silicon layer 14 forming a conventional gate electrode has the crystal orientation of the crystal grains arranged in a plurality of plane orientations. That is to say, polycrystal silicon layer 14 has crystal grains of (110) plane orientation and crystal grains of (111) plane orientation in the example of FIG. 8. Polycrystal silicon layer 14 is doped with phosphorus.
FIGS. 9A-9D are sectional views of a conventional P channel MOS transistor for explaining the manufacturing process thereof. Referring to FIG. 9A, element isolation oxide films 12 are formed on an N type silicon substrate 11 with a predetermined distance therebetween for element isolation. A gate oxide film 13 is formed on N type silicon substrate 11 and element isolation oxide films 12. Referring to FIG. 9B, a polycrystal silicon layer 14 having phosphorus doped is formed on gate oxide film 13. Polycrystal silicon layer 14 serves as a gate electrode. This polycrystal silicon layer 14 is formed of crystal grains having different plane orientations, as described above. Referring to FIG. 9C, gate oxide film 13 and polycrystal silicon layer 14 are patterned by etching using a resist pattern (not shown). Thus, a gate electrode having the structure of the present embodiment is obtained. Referring to FIG. 9D, B.sup.+ ions 16 are implanted to form p.sup.+ impurity regions 15, using polycrystal 0 silicon layer 14 as a mask. A conventional P channel MOS transistor is formed according to the above described manufacturing process. Polycrystal silicon layer 14 eventually is formed of crystal grains having two crystal orientations of (110) and (111) plane orientations, as described above.
In a conventional P channel MOS transistor, p.sup.+ impurity regions 15 are formed in self-alignment by implanting B.sup.+ ions using polycrystal silicon layer 14 which becomes a gate electrode as a mask.
Because the above described polycrystal silicon layer 14 is formed of crystal grains having crystal orientations different from each other, there was a problem that B.sup.+ ions pass through polycrystal silicon layer 14 if the crystal orientation is identical to the implantation angle of the ions. This problem is called a channeling phenomenon. The implantation of B.sup.+ ions right beneath the gate electrode due to channeling phenomenon induces problems that will be explained hereinafter. The channel region between p.sup.+ impurity regions 15 serving as the source/drain is likely to become conductive (channel leak) which is adverse to the proper operation. The generation of channel leak induces a problem that leak current and erroneous operation are increased of the entire semiconductor device. There was also a problem that the threshold voltage rises concerning the transistor characteristic of the P channel MOS transistor.
A conventional P channel MOS transistor had a difficulty in preventing effectively generation of erroneous operation and deterioration of the characteristic of a transistor, in the case where an impurity region is formed in self-alignment by ion implantation using a gate electrode as a mask.